PRODUCT SPECIFICATION
ML4824
REV. 1.0.6 11/7/03
11
In the case of leading edge modulation, the switch is turned
OFF right at the leading edge of the system clock. When the
modulating ramp reaches the level of the error amplier
output voltage, the switch will be turned ON. The effective
duty-cycle of the leading edge modulation is determined
during the OFF time of the switch. Figure 5 shows a leading
edge control scheme.
One of the advantages of this control teccnique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to minimize
the momentary no-load period, thus lowering ripple
voltage generated by the switching action. With such
synchronized switching, the ripple voltage of the rst stage
is reduced. Calculation and evaluation have shown that the
120Hz component of the PFCs output ripple voltage can be
reduced by as much as 30% using this method.
 Figure 4. Typical Trailing Edge Control Scheme.
 Figure 5. Typical Leading Edge Control Scheme.
RAMP
VEAO
TIME
VSW1
TIME
REF
EA

+

+
OSC
DFF
R
D
Q
Q
CLK
U1
RAMP
CLK
U4
U3
C1
RL
I4
SW2
SW1
+
DC
I1
I2
I3
VIN
L1
U2
REF
EA

+

+
OSC
DFF
R
D
Q
Q
CLK
U1
RAMP
CLK
U4
U3
C1
RL
I4
SW2
SW1
+
DC
I1
I2
I3
VIN
L1
VEAO
CMP
U2
RAMP
VEAO
TIME
VSW1
TIME
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